The present invention pertains generally to electrical circuit testing and more particularly to a capacitive probe assembly with flex circuit for use in printed circuit board testing.
Capacitive coupling sensors are used in the testing of electrical circuits for the identification of open-circuit faults. These sensors are regularly used to determine whether the leads of semiconductor components are present and properly soldered or otherwise connected to a printed circuit board. Typical implementation of capacitive probe assemblies that implement a capacitive sensor may be found in the following references, each of which is incorporated herein by reference for all that it teaches: U.S. Pat. No. 5,498,964, to Kerschner et al., entitled “Capacitive Electrode System for Detecting Open Solder Joints in Printed Circuit Assemblies”, U.S. Pat. No. 5,124,660 to Crook et al., entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”, U.S. Pat. No. 5,254,953 to Crook et al., entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”, and U.S. Pat. No. 5,557,209 to Crook et al., entitled “Identification of Pin-Open Faults By Capacitive Coupling Through the Integrated Circuit Package”.
FIG. 1 shows a portion of a prior art printed circuit board open-fault test circuit 300 which illustrates the typical use and operation of a capacitive sensor. As shown in FIG. 1, the open-fault test circuit 300 includes a signal source 330, which supplies a signal, typically eight kiloHertz (8 KHz) at two hundred millivolts (120 mV). The output of signal source 330 is connected to a printed circuit board trace 332, which is connected to the integrated circuit lead under test 12 at 334. The connection of the signal source 330 to the trace 332 is typically made through a bed of nails connection pin. To reduce the effects of stray capacitive coupling between leads which interferes with the measurement of the lead under test, all leads not being currently tested are preferably grounded.
A capacitive test probe 320 is placed on top of the integrated circuit package 10. A thin dielectric (not shown) may be placed between the component package 10 and the test probe 320. The capacitive test probe 320 is connected to a measuring device 335, such as an ammeter, a voltmeter or computing means to compute the effective capacitance. When the measurement falls outside predetermined limits a determination is made that the lead being tested is diagnosed as being open.
When the test is performed, the signal source 330 is activated and applied to trace 332 on the printed circuit board which should be attached to the lead being tested 12 at location 334. The source signal should then pass to the lead 12 of the component 10. Through capacitive coupling, the signal is passed to the capacitive test probe 320 and then to the measuring device 335. If the measured parameter falls within predetermined limits, then the lead 12 is connected to the trace 332 at location 334. If the lead 12 is not connected at location 334 or if the wire trace 332 is broken, a smaller signed will be conducted to the capacitive test probe 320 and the threshold level of the signal will not be measured by the measuring device 335, indicating that an open fault is present.
FIG. 2 shows a top, front perspective view, and FIG. 3 shows a side cut-away view, of a prior art test probe, namely a TestJet® probe, manufactured by Agilent Technologies of Palo Alto, Calif., the assignee of interest of the present invention. Referring now to FIGS. 2 and 3, the capacitive test probe 320 includes a capacitive plate 323, a guard plate 324, an active buffer circuit 326, a signal electrode spring pin 321a and a guard electrode spring pin 321b. The capacitive plate 323 and the guard plate 324 are separated by a dielectric 325. During test, the capacitive plate 323 forms a capacitor with a conductive plate of the component (e.g., one of integrated circuit leads 313a-313h in FIG. 4) under test. The capacitive plate 323 of the test probe 320 is electrically coupled to an active buffer circuit 326, which is located on the top surface of the dielectric and surrounded by the guard plate 324. The capacitive plate 323 is connected to the buffer circuit 326 at a location 327 (see FIG. 3). The amplification of the signal by the buffer circuit 326 which is in close proximity to the capacitive plate 323 where the signal is received helps to significantly optimize the signal to noise ratio, thereby decreasing the effect of system noise and stray capacitance.
A groove 328 is etched all the way around the area of the buffer circuit 326 to electrically isolate the buffer circuit 326 from the guard plate 324. The buffer circuit 326 is electrically connected by a pin in socket connector 322b to a standard signal electrode spring pin 121a, which acts as an electrical coupling means to a measuring device. The guard plate 324 is electrically connected by a pin in socket connector 322b to a guard electrode spring pin 121b, which electrically couples the guard plate to system ground or a controlled voltage source.
FIG. 4 shows a top cut away view of the integrated circuit component 10 and the capacitive test probe 320. FIGS. 1 and 4 illustrate how the capacitive coupling occurs between the capacitive test probe 320 and the leads 12 of the integrated circuit. Referring now to FIGS. 1 and 4, the integrated circuit package 10 contains an integrated circuit die 11. The integrated circuit die 11 contains connections, however, these connections must be made to the outside of the integrated circuit package 10. Therefore, the lead 12 is connected to an internal conductor 13 that connects the lead 12 to a location just adjacent to the integrated circuit 11. There a small wire (bond wire) spans between the conductor 13 and a location on the integrated circuit 11. Similar connections are made to all the other leads of the integrated circuit package 10.
The conductor 13 forms an electrically conductive plate, which acts as one plate of a capacitor. The other plate of the capacitor is formed by a capacitive plate 323 of the capacitive test probe 320 (see FIG. 1). Although the capacitor created in this manner is small, it is sufficient to conduct a signal between the lead 12 and the capacitive test probe 320 when the test probe 320 is aligned over the top of the integrated circuit package 10, as shown in FIGS. 1 and 4.
It would be desirable to have a method and apparatus for obtaining multiple capacitively coupled signal measurements simultaneously. Although the size of a capacitive probe assembly may be made to be quite small, it cannot compete with the spacing of integrated circuit package test leads. Accordingly, in order to test all integrated circuit package test leads yet reduce or eliminate complicated robotic circuitry for positioning the probe over a given pin, it would also be desirable to be able to place multiple capacitive sensing probes on one capacitive probe assembly.